Effective physical-based propagation delay calculation method for high-speed transceivers in high-density FPGA packages

This paper describes an analytical methodology to calculate every high-speed transceiver pins propagation time in high-density FPGA packages efficiently. This technique split the transceiver channels in the sophisticated multi-layer package design structure into horizontal and vertical transmission paths with 3-D full-wave electromagnetic modeling to provide accurate parametric solutions. Full package timing delay information is constantly demanded by end customers for board skew compensation and system timing analysis. Hence, the primary objective is to propose a simple approach to reduce the turn-around time by 3 to 5x while achieving high accuracy of the package transceivers propagation delay. The proposed methodology is able to achieve high accuracy with less than 1 picoseconds (ps) difference comparing to a complete bump-to-ball 3-D full-wave simulation model extraction. The accuracy of the proposed technique is well proven in this paper with real bare substrate measurement using Time Domain Reflectometry (TDR) technique. The measurement results show less than 5ps difference only. Hence, the methodology discussed in this paper is highly efficient in terms engineering cost, time and quality as it is applicable to various die-package combinations in a highly competitive FPGA market to meet different customer requirements.