DocumentCode :
3750202
Title :
Co-process technology of the TSV and embedded IC for 3D heterogeneous IC integration
Author :
Jong-Min Yook;Seong-Ryul Kim;Won-Cheol Lee;Dong-Su Kim;Jun-Chul Kim
Author_Institution :
Packaging Research Center, Korea Electronics Technology Institute, 68 Yatap-dong, Bundang-gu, Seongnam-si, Gyeonggi-do, 463-816, South Korea
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a co-process technology of the through silicon via (TSV) and embedded IC for 3D heterogeneous IC integration. Heterogeneous ICs are embedded by using silicon cavities and advanced TSVs for 3D interconnection are integrated in the interposer at the same time. Organic lamination is used to fill the gap and make an insulation layer. A laser drilling process is used to make via interconnections of the inserted IC and through silicon via. The hole-size realized by using a laser machine is 70 μm. The co-processed TSV shows very low insertion losses owing to thick laminated organic. Its insertion loss is lower than 0.1 dB at 10 GHz. To demonstrate the interposer technology, a RF switch LNA module is designed and realized by using the interposer technology. Thin film passive devices are integrated on the silicon interposer and heterogeneous ICs such as a SPDT switch and LNA IC are embedded. The fabricated module thickness is only 180 μm and it is 3D stackable.
Keywords :
"Silicon","Switches","Cavity resonators","Three-dimensional displays","Lamination","Integrated circuit interconnections"
Publisher :
ieee
Conference_Titel :
Electronics Packaging and Technology Conference (EPTC), 2015 IEEE 17th
Type :
conf
DOI :
10.1109/EPTC.2015.7412306
Filename :
7412306
Link To Document :
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