Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows

In this paper, we describe the importance of carefully selecting the wafer backside processes in 3D stacked IC process flows. In particular, we report on the impact of TSV Via-middle reveal and backside passivation processes on the C-V characteristic of the TSV. The cause of anomalous C-V inversion of the TSV capacitor is explained and a solution is given to avoid this effect.