Title :
Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology
Author :
F.X. Che;David Ho;Mian Zhi Ding;Xiaowu Zhang
Author_Institution :
Institute of Microelectronics, A?STAR (Agency for Science, Technology and Research) 11 Science Park Road, Singapore Science Park II, Singapore 117685
Abstract :
Fan-out wafer-level-packaging (FO-WLP) technology gets more and more significant attention with its advantages of small form factor, higher I/O density, cost effective and high performance for wide range application. However, wafer warpage is still one critical issue which is needed to be addressed for successful subsequent processes for FO-WLP packaging. In this study, methodology to reduce wafer warpage of 12" wafer at different processes was proposed in terms of geometry design, material selection, and process optimization through finite element analysis (FEA) and experiment. Wafer process dependent modeling results were validated by experimental measurement data. Solutions for reducing wafer warpage were recommended. Key parameters were identified based on FEA modeling results: thickness ratio of die to total mold thickness, molding compound and support wafer materials, dielectric material and RDL design.
Keywords :
"Semiconductor device modeling","Compounds","Silicon","Packaging","Electromagnetic compatibility","Mathematical model","Compression molding"
Conference_Titel :
Electronics Packaging and Technology Conference (EPTC), 2015 IEEE 17th
DOI :
10.1109/EPTC.2015.7412319