DocumentCode :
3750238
Title :
Development of fluxless flip chip reflow process for high density flip chip interconnect
Author :
Sharon Pei-Siang Lim;Mian Zhi Ding;Jong Kai Lin;Vempati Srinivasa Rao
Author_Institution :
Institute of Microelectronics, A?STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II S(117685)
fYear :
2015
Firstpage :
1
Lastpage :
6
Abstract :
In flip chip technology, flux is widely used to clean the surface of the solder bumps and the surfaces to be soldered for good wetting of the solder bumps on the conductive bond pads [1]. Moreover, flux helps to keep the flipped chip in position and hold it during die placement and the subsequent reflow process. However, this flux-containing reflow can cause problems and inconveniences. For example, volatile materials are generated when organic fluxes decompose during heating. These volatiles could be trapped in the molten solder and form voids, which degrade mechanical and electrical properties of the solder joints, and affect the subsequent chip bonding process [2]. In addition, flux residues adversely affect underfill interfacial adhesion in the flip chip assembly process. Flux residues must therefore be removed, which is typically done through post-reflow cleaning. With no-clean fluxes, which include a small amount of activators to minimize residues, there is a tradeoff between reduced residues and diminished flux performance. Because of the problems associated with organic fluxes, there is a need to study the fluxless solder reflow process [3]. In this paper, we study the fluxless flip chip reflow process and evaluated the reliability performance for 2 different test dies onto the 100um thin 2.5D TSV Si interposer using a temporary adhesive material. The assembled sample is then subjected to a lead-free reflow profile in vacuum oven with forming acid. One advantage of the temporary adhesive material is that it will evaporate at reflow temperature. Results showed that both test dies passed moisture sensitivity level test level 3 under Jedec standard J-STD-020 (30°C/60%RH) for 192 hours without any underfill delamination.
Keywords :
"Flip-chip devices","Bonding","Substrates","Soldering","Ovens","Cleaning"
Publisher :
ieee
Conference_Titel :
Electronics Packaging and Technology Conference (EPTC), 2015 IEEE 17th
Type :
conf
DOI :
10.1109/EPTC.2015.7412342
Filename :
7412342
Link To Document :
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