Enhance TCOB life for wafer level package with a new leadfree solder alloy

Driven by minimized package size, cost as well as performance, wafer level package (WLCSP) is currently one of the fastest growing segments in the semiconductor packaging industry. Not as plastic BGA with a substrate interposer, WLP is a silicon chip directly mounted on printed circuit board (PCB) board. The large CTE(coefficient of thermal expansion) mismatch between silicon and organic leads to very high solder joint stress, which will decrease TCOB(thermal cycling on board) life for solder joints. Thus TCOB life is one of the main challenges on WLCSP, especially with large die. This study is focused on enhancement of TCOB life for WLCSP in the face of increasing die-size requirements. Several WLCSPs with different size are selected as test vehicles. Mechanical simulation has been carried out to understand the TCOB behavior and help to optimize the package design. TCOB test has been done to quantify the real life and to validate the simulation models for current SAC-N solder. To enhance the life margin, especially for large size package, a new Solder SAC-Q has been evaluated. Initial results indicate SAC-Q is showing remarkable TCOB improvement with acceptable drop test performance. Simulation model has been built up to understand the different behavior between SAC-Q and SAC-N. Much lower plastic work in SAC-Q correlates well to its longer life than SAC-N.