A capacitor mismatch and gain insensitive 1.5-bit/stage pipelined A/D converter

Author

Keramat, M. ; Tao, Z.

Author_Institution

Electr. & Comput. Eng. Dept., Connecticut Univ., Storrs, CT, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

48

Abstract

In this paper, an architecture for the switched capacitor multiply-by-two amplifier for the 1.5-bit per stage pipelined analog-to-digital (A/D) converter is presented. The gain of the proposed architecture is insensitive with respect to the capacitor mismatch as well as finite gain, offset voltage, and 1/f noise of operational amplifier. The switch-induced error can be further suppressed by fully differential structure. This architecture with small modifications can also be used in high-resolution recycling A/D converters where precise multiply-by-two is required

Keywords

1/f noise; analogue-digital conversion; operational amplifiers; pipeline processing; switched capacitor networks; capacitor mismatch; finite gain; fully-differential architecture; l/f noise; offset voltage; operational amplifier; pipelined analog-to-digital converter; recycling analog-to-digital converter; switch-induced error; switched capacitor multiply-by-two amplifier; Analog-digital conversion; Clocks; Operational amplifiers; Recycling; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Switching converters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951585

Filename

951585