Title :
A multi-level netlist partitioning approach to hierarchical layout design of analog ICs
Author :
Wu, P.B. ; Mack, R.J. ; Massara, R.E.
Author_Institution :
Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
Abstract :
An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results
Keywords :
analogue integrated circuits; circuit layout CAD; integrated circuit layout; network routing; analog IC; area efficiency; built-in move operators; hierarchical layout design; multi-level netlist partitioning algorithm; routability; Algorithm design and analysis; Circuit simulation; Costs; Degradation; Design engineering; MOSFETs; Partitioning algorithms; Simulated annealing; Solid modeling; Systems engineering and theory;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951601
