A calibration algorithm for a 16-bit multi-path pipeline ADC

Author

Younis, Ahmed ; Navin, Venkata ; Hassoun, Marwan

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

158

Abstract

Presents a calibration algorithm to design and, characterize a 16-bit analog-to-digital converter, (ADC). The main goal is to build a 16-bit multi-path pipeline ADC with a very high spurious free dynamic range, (SFDR), operating around 20 MHz. The multi-path pipeline ADC consists of 4 time-interleaved pipeline ADCs. With channel calibration using the accuracy bootstrapping technique and global calibration using normalization

Keywords

analogue-digital conversion; bootstrap circuits; calibration; integrated circuit measurement; pipeline processing; 16 bit; 20 MHz; accuracy bootstrapping technique; analog-to-digital converter; calibration algorithm; channel calibration; global calibration; multi-path pipeline ADC; normalization; spurious free dynamic range; time-interleaved pipeline ADCs; Algorithm design and analysis; Analog-digital conversion; Calibration; Circuits; Digital signal processing; Digital signal processing chips; Dynamic range; Interleaved codes; Pipelines; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951609

Filename

951609