Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with compact test sets

It was recently suggested by Jone and Das that given a multiple-output combinational circuit, a parity bit signature for exhaustive testing of VLSI circuits can be generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. Based on the aforesaid concepts of Jone and Das, this paper proposes a multiple-output parity bit signature for built-in self-testing of VLSI circuits using nonexhaustive or compact test sets. The feasibility of the developed approach is demonstrated by extensive simulation experiments on ISCAS 85 combinational benchmark circuits using simulation programs FSIM, ATALANTA, and COMPACTEST, showing a high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead