A 216GHz 0.5mW transmitter with a compact power combiner in 65nm CMOS

This paper presents the design and measurements of a 216GHz, 0.5mW transmitter using 65nm bulk CMOS process. The transmitter is formed of an amplifier-multiplier chain, where the power amplifier delivers a P_sat =16dBm at 110GHz to a passive frequency doubler. The PA stage employs a novel single-ended to 2-way differential power combiner based on vertically coupled transmission lines. A passive frequency doubler implemented using MOS varactors follows the PA. The 216GHz transmitter delivers a maximum of 0.5mW at 216GHz with a 2.8% bandwidth, while consuming 500mW from a 1V DC supply. The chip, implemented in thin BEOL seven metal ST-65nm CMOS process, occupies a total area of 0.88mm².