DocumentCode :
3750606
Title :
A 20% locking range and −125dBc/Hz phase noise quotient frequency synthesizer suitable for multiband millimeter-wave applications
Author :
R. X. Zhang;C. Q. Shi;T. Y. He
Author_Institution :
Institute of Microelectronic Circuits and Systems, East China Normal University, Shanghai 200062, China
Volume :
2
fYear :
2015
Firstpage :
1
Lastpage :
3
Abstract :
This paper describes the design of a PLL-based and integer-N quotient frequency synthesizer (QFS) suitable for V, E and W multiband mm-wave applications. The complementary NMOS and PMOS dual-injection structure with independent gate bias and co-tuning technology are adopted to improve injection efficiency and extend frequency locking range of ILFD. The ameliorated pseudo-differential cascode structure is applied in buffer stages to enhance gain and stability performance. The frequency synthesizer, fabricated in low cost 0.13μm CMOS process, can provide over +1.5dBm output power at 50ohm load within a wide frequency range from 27.38 to 33.5GHz and the closed-loop phase noise of -111.25 to -110.2dBc/Hz at 10MHz offset from carrier frequency and -125dBc/Hz at 100MHz offset while drawing 70mA current (not including testing buffers) from 2.5V power supply.
Keywords :
"Frequency synthesizers","Decision support systems","Phase noise","CMOS integrated circuits","MOS devices","Logic gates","Testing"
Publisher :
ieee
Conference_Titel :
Microwave Conference (APMC), 2015 Asia-Pacific
Print_ISBN :
978-1-4799-8765-8
Type :
conf
DOI :
10.1109/APMC.2015.7413091
Filename :
7413091
Link To Document :
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