Low power digital CMOS buffer systems for driving highly capacitive interconnect lines

Author

Secareanu, Radu M. ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

362

Abstract

A CMOS buffer system to drive highly capacitive interconnect lines with reduced power dissipation is presented. The speed of the proposed buffer system is equivalent to the speed of an optimal tapered buffer that drives an equivalent capacitive load, while the power dissipation and area are significantly reduced. The proposed buffer system also provides low switching noise and improved chip reliability by decreasing the likelihood of electromigration and on-chip hot spots

Keywords

CMOS digital integrated circuits; buffer circuits; capacitance; delays; driver circuits; integrated circuit interconnections; integrated circuit noise; integrated circuit reliability; low-power electronics; chip reliability; highly capacitive interconnect lines; low power digital CMOS buffer systems; low switching noise; power dissipation; Capacitance; Circuit noise; Drives; Electromigration; High definition video; Integrated circuit interconnections; Power dissipation; Power system interconnection; Power system reliability; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951661

Filename

951661