SOI for VLSI clock-powered processors

Author

Tzartzanis, Nestoras ; Athas, William

Author_Institution

Fujitsu Labs. of America, Sunnyvale, CA, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

374

Abstract

A 0.35 μm bulk CMOS VLSI processor chip is compared with two SOI implementations (0.25 μm and 0.50 μm). The 0.35 μm bulk chip dissipates 16 mW at 69 MHz and the 0.25 μm SOI chip dissipates 28 mW at 73 MHz. The higher dissipation of the SOI chips was due to the layout conversion process. The area increased by 2.3× and 6.3× for the clock networks of the SOI chips but the measured clocked capacitance only increased by 1.6× and 1.7×. This result indicates that removal of the grounded substrate greatly reduced the effective clocked capacitance per unit area for the SOI chips

Keywords

CMOS digital integrated circuits; VLSI; capacitance; high-speed integrated circuits; integrated circuit layout; microprocessor chips; silicon-on-insulator; timing; 0.25 micron; 0.35 micron; 0.5 micron; 16 mW; 28 mW; 69 MHz; 73 MHz; SOI implementations; Si; VLSI clock-powered processors; VLSI processor chip; bulk CMOS implementation; clock networks; clocked capacitance; grounded substrate; layout conversion process; power dissipation; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Laboratories; Parasitic capacitance; Power dissipation; Semiconductor device measurement; Silicon on insulator technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951663

Filename

951663