Title :
A VLSI architecture for soft-output PR4 detection
Author :
Gross, Warren J. ; Gaudet, Vincent C. ; Gulak, P. Glenn
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
A 0.35 μm 3-level metal CMOS ASIC is developed for forward-backward soft-output detection of Class-IV partial response signaling. The novel, low-complexity architecture uses a difference metric and a computational kernel implemented as a limiter. The chip was verified to operate at 20 MHz (20 Mbps), the highest speed of our IC tester. Simulations predict operation of up to 150 Mbps
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; disc drives; high-speed integrated circuits; partial response channels; signal detection; 0.35 micron; 20 MHz; 20 to 150 Mbit/s; 3-level metal CMOS ASIC; Class-IV partial response signaling; VLSI architecture; computational kernel; difference metric; forward-backward soft-output detection; limiter; low-complexity architecture; soft-output PR4 detection; Bit error rate; Computational modeling; Computer architecture; Decoding; Detection algorithms; Detectors; Educational institutions; Kernel; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951672
