Signal integrity considerations for the PCB implementation of multi-gigabit SERDES links

Serial communication links have become indispensable in data transfer, primarily in chip to chip communications over printed circuit boards and backplanes. Data rates of 10 Gbps are common today and rates as high as 25 Gbps are feasible. Use of advanced signal processing techniques in SERDES (Serializers/Deserializers) such as transmit pre-emphasis and receive equalization have enabled reliable operation of these links on channels that can be severely impaired. Yet, fundamental limitations remain and certain shortcomings in channel characteristics cannot be corrected. Therefore, it is important to pay close attention to the Printed Circuit Board (PCB) layout to ensure robust error free transmission of high speed serial data. This paper presents a description of factors that affect link performance and methods for controlling them at the PCB level.