Design for PLL of Maintenance System in Satellites

Satellite navigation and positioning system has much to do with the fields such as life, scientific research and military industry. In order to ensure long-term and reliable working onboard, the redundancy design with more atomic clocks has been adopted. When the chief clock doesn´t operate properly, a swtich from the chief clock to one warm spare clock will smoothly take place to ensure the stable output. Due to the switching between the atomic clocks, phase and frequency hopping is bound to existing, so the switching signal must keep steady through PLL (phase locked loop). The traditional analog narrow-band integrator has complex composition, thermal drift. The ideal bandwidth is about 10~100mHz, within that the analog narrow-band PLL needs 10 minutes to lock. The frequency hopping may lead to the PLL unlocked. The paper adopts digital-PLL. It has little drift and ad-justing the loop bandwidth by feedback to lock fastly and reduce greatly the phase noise of the output. In this paper, the two tuning voltage mode with 24 bit resolution realizes frequency locking precision to the small coefficients of 10^-12 order.