Title :
Design of a faithful LNS interpolator
Author_Institution :
Univ. of Manchester Inst. of Sci. & Technol., UK
Abstract :
A design is given for a quadratic interpolator needed by the logarithmic number system (LNS). Unlike previous LNS designs that have attempted to produce results consistently better than a floating-paint representation of the same word size (32 bits), the design goal is to minimize memory requirements and system complexity, at the expense of a slight increase in approximation error. Simulation results have shown this goal causes only a modest impact on overall accuracy, but the memory savings are significant. Despite a slight increase in error compared to prior LNS implementations, on average, the error is still less than conventional number representations satisfying the IEEE-754 standard. Proposed applications for the interpolator include multimedia, signal processing, graphics and reconfigurable computing
Keywords :
digital arithmetic; interpolation; IEEE-754 standard; approximation error; faithful LNS interpolator design; graphics; logarithmic number system; memory requirements; multimedia; quadratic interpolator; reconfigurable computing; signal processing; simulation; system complexity; Application software; Computer errors; Computer graphics; Computer industry; Costs; Floating-point arithmetic; Manufacturing industries; Multimedia computing; Signal processing; Signal processing algorithms;
Conference_Titel :
Digital Systems Design, 2001. Proceedings. Euromicro Symposium on
Conference_Location :
Warsaw
Print_ISBN :
0-7695-1239-9
DOI :
10.1109/DSD.2001.952321