Transistor chaining with integrated dynamic folding for 1-D leaf cell synthesis

In this paper, a new method of transistor chaining for 1-D automatic leaf cell synthesis is presented. The method allows synthesis of cells suitable for row-based layouts with no restrictions imposed on network topologies/transistor sizes. The novelty of the solution arises from transistor chaining with integrated dynamic transistor folding. We provide the theoretical analysis of transistor folding, then formulate the problem and solve it using the computational model made after that of Bar-Yehuda et al. (1989). The model serves us as a basis for the novel algorithm constructed using the dynamic programming technique. The preliminary experiments show that the method reaches good quality chainings and the dynamic folding leads to further elimination of the diffusion gaps comparing to the recent results of other researchers. This results in the reduction of the layout width as well as the improvement of its manufacturability and quality