Title :
Verification of memory access protocols in behavioral synthesis
Author :
Koch, Gernot ; Kim, Taewhan ; Genevriere, Reiner
Author_Institution :
Synopsys Inc, Mountain View, CA, USA
Abstract :
In behavioral synthesis, a memory is viewed as an abstract construct which hides the detailed implementation of the memory. In this paper, we propose a systematic methodology of verifying the correctness of the memory wrapper. The automation of our solution shortens the verification time significantly in contrast to simulating memory accesses in the context of full design, which is quite complex and time-consuming
Keywords :
formal verification; hardware description languages; high level synthesis; memory protocols; VHDL; behavioral synthesis; high-level abstraction; memory access protocols verification; memory wrapper correctness; read-read pipeline; systematic methodology; verification time; Access protocols; Automatic testing; Computer science; Context modeling; Hardware design languages; Information technology; Pipeline processing; Read-write memory; System testing; Wrapping;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.952916
