Title :
Design of 1.5V-3GHz CMOS two stages three loops chained VCO
Author :
Yu, Hwa Yeal ; Oh, Se Hoon ; Chung, Jin Won ; Yoon, Kwang Sub
Author_Institution :
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
Abstract :
This paper proposes a new delay cell for operating in high frequency and multi chained two stage VCO to improve phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing and the newly VCO is operating in high frequency. The PFD circuit designed to prevent fluctuation of charge pump circuit under the locking condition. Simulation results show that the tuning range of proposed VCO is wide at 1.8GHz~3.2Ghz and power dissipation is 0.6mW
Keywords :
CMOS analogue integrated circuits; circuit tuning; delay circuits; integrated circuit noise; phase detectors; phase locked loops; phase noise; timing jitter; voltage-controlled oscillators; 0.6 mW; 1.5 V; 3 GHz; CMOS circuit design; PFD circuit; charge pump circuit; delay cell; high-frequency VCO; multi-chained two-stage three-loop architecture; phase noise; power dissipation; timing jitter; transition spacing; tuning range; Charge pumps; Circuit optimization; Circuit simulation; Delay; Fluctuations; Phase frequency detector; Phase noise; Timing jitter; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.952924
