A reconfigurable architecture for a class of digital signal/image processing applications

This paper aims to present a reconfigurable architecture for a class of digital signal/image processing applications. The architecture exploits the speed of hardware and the flexibility of programmable processors (PP). The proposed architecture consists of a processor control block (PCB) and a reconfigurable processing block (RPB). The PCB consists of a processor and memory modules. The RPB consists of a number of reconfigurable FPGA that are used for executing image/digital signal processing functions. The PCB is responsible for fetching and decoding signal/image processing functions (SPI) like SMOOTH <data>, FIR<data, data>, EDGE-DETECTION <data>, DCT <data>, IDCT <data> etc. After decoding, the PCB sends the control data and information to the RPB. Upon receiving the control signals and data, the RPB starts executing an SPI. After the execution of an SPI, control is returned back to the PCB for fetching and decoding of the next SPI. Execution of SPI by this architecture is analogous to the execution of instructions by conventional general purpose processors. During the execution of an SPI by RPB, PCB can be involved in executing other work. The overhead involved in reconfiguring the FPGA has been reduced to zero by overlapped reconfiguration operations. There is also an incredible saving in hardware as the same FPGA is used as different processing blocks. In addition, the architecture is scalable because new modules can be added or existing modules can be modified very easily by adding or changing the configuration bitstream for the SPI