Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints

This paper presents a test infrastructure development and test scheduling strategy for 3D-SICs under resource (test pins and TSVs) and power constraints. Depending upon the various scheduling restrictions, two test scheduling strategies have been proposed with an objective to minimize the overall test time (TT) of the stack. A step-by-step approach deals with the individual dies separately and develops power-restricted test schedules for each die and finally decides test concurrency between the dies satisfying the resources and power limits of the stack. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation and power distribution to individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of the SIC. Another integrated approach uses PSO to generate power-constrained test schedule of the entire SIC in a single optimization step. Integrated approach produces better results than the step-by-step approach because of its higher flexibility with lesser restrictions. User may select any of the scheduling strategies depending upon the scheduling criteria.