A register-transfer level BIST partitioning approach for ASIC designs

Various approaches have been proposed to enhance the testability of VLSI by incorporating extra testability features. Recent advances in VLSI technology are motivating changes in the traditional methods of design and test, leading to the integration of design and test activities. Testability, defined as the facility to generate and apply test, is added as a new constraint to the synthesis process and design modifications are proposed to improve testability. One popular design for testability methodology is built-in self-test (BIST) techniques, where pseudo-random pattern generators (RTPG) generate and supply test patterns and multi-input signature registers (MISR) compress test responses. These techniques involve modification of the hardware on the chip so that the chip has the capability to test itself. The goal of this paper is to develop a new improvement method with BIST technique at register transfer level (RTL)