FPGA-based Acceleration of Deep Neural Networks Using High Level Method

Deep neural network (DNN) is becoming more and more applied in data center applications such as speech recognition, image search, etc. However, the training in DNN is very time-consuming because of its deep structure. This paper presents FPGA-based acceleration of deep neural networks using a high level method and proposes a parallel optimizing strategy using the Kintex-7 FPGA board´s features. Experimental results show that it can increase the utilization of FPGA computation units with low mini-batch size and reduce the transfer cost effectively. The optimized algorithm achieves up to 17.65x higher performance than CPU.