• DocumentCode
    3757157
  • Title

    Eliminating Cascading Stall on Hardware Transactional Memory

  • Author

    Sho Miyake;Keisuke Mashita;Ryohei Yamada;Tomoaki Tsumura

  • Author_Institution
    Nagoya Inst. of Technol., Nagoya, Japan
  • fYear
    2015
  • Firstpage
    147
  • Lastpage
    153
  • Abstract
    Multi-core processors are equipped in almost every computer systems from smartphones to high-end server machines, and shared memory programming becomes increasingly important for programmers to utilize the multi-core systems. Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and this leads to poor scalability. To make up for the shortcomings of lock, transactional memory (TM) is proposed and widely studied. On TMs, transactions are executed speculatively while any conflicts do not occur on shared variables. However, wasteful re-executions and waits can cause low concurrency and drastic performance degradation. In this paper, we propose a method for resolving Cascading Stall which is one of the main factors of low concurrency on TM. The result of the experiment shows that the method can reduce execution time 56.5% in maximum and 11.1% in average with 16 threads.
  • Keywords
    "Hardware","Instruction sets","Concurrent computing","Memory management","Synchronization","Multicore processing","System recovery"
  • Publisher
    ieee
  • Conference_Titel
    Computing and Networking (CANDAR), 2015 Third International Symposium on
  • Electronic_ISBN
    2379-1896
  • Type

    conf

  • DOI
    10.1109/CANDAR.2015.100
  • Filename
    7424703