Title :
Fast capacitance extraction of conductors embedded in a layered medium
Author :
Pan, Y.C. ; Chew, W.C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
A new fast multipole method for a stratified medium is presented. The algorithm, which has O(N) computational and memory complexity, can be applied to the general capacitance extraction problem of conductors embedded in a stratified medium
Keywords :
VLSI; capacitance; circuit complexity; circuit layout CAD; integrated circuit interconnections; integrated circuit modelling; poles and zeros; O(N) computational complexity; O(N) memory complexity; VLSI; circuit layouts; embedded conductors; fast capacitance extraction; multiconductor structures; multipole method; parasitics model; stratified medium; Capacitance; Computational complexity; Computational electromagnetics; Conductors; Dielectrics; Embedded computing; Inductance; Integral equations; Tree data structures; Very large scale integration;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2001
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-7024-4
DOI :
10.1109/EPEP.2001.967637
