• DocumentCode
    3757567
  • Title

    Design of a CMOS Three-Stage Operational Amplifier for ALD

  • Author

    Yang Guang;Cui Linhai;Huang Hai

  • Author_Institution
    Harbin Univ. of Sci. &
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    48
  • Lastpage
    51
  • Abstract
    In this paper, a three-stage operational amplifier with low-power consumption for ALD has been designed. Based on TSMC 0.55μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that the proposed op-amp has more than 100dB open loop gain, meanwhile the static power consumption is less than 900μw. The circuit´s phase margin is 103degrees, CMRR is 51dB and power supply rejection ratio is 57dB.
  • Keywords
    "Operational amplifiers","CMOS integrated circuits","Power demand","Layout","Simulation","Negative feedback"
  • Publisher
    ieee
  • Conference_Titel
    Advanced Communication and Networking (ACN), 2015 Seventh International Conference on
  • Print_ISBN
    978-1-4673-7954-0
  • Type

    conf

  • DOI
    10.1109/ACN.2015.15
  • Filename
    7425544
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3757567