Testability features of a single photon counting hybrid pixel detector readout circuit with charge sharing elimination algorithm

The paper presents the specific testability features included in the design of a single photon counting hybrid pixel detector readout circuit built in the 40nm CMOS. The readout integrated circuit consists of a 18×24 pixel matrix with a pitch of 100 μm. Each pixel comprises of a charge sensitive amplifier, two shapers, two discriminators, eight comparators, tens of inter-pixel connections and a digital functionality allowing elimination of charge sharing effect using the C8P1 algorithm. Due to the high complexity of the chip, the extended testability features, allowing verification of single blocks and suitable for very small areas, are required. The paper presents the single pixel architecture with highlights of certain testability blocks, their description, area estimations and exemplary use cases.