High data rate 60 GHz CMOS transceiver design

This paper discusses 60 GHz CMOS transceiver design focusing on the techniques to increase the transmission data rate. Basic design key points are the increase of bandwidth, the increase of SNR of ADC, and the decrease of phase noise in quadrature oscillator. Thus we selected the direct conversion architecture and used multi-cascading RF amplifiers. The resistive feedback amplifier is effective to realize the wideband impedance matching. The injection locking method is applied to the 60 GHz quadrature oscillator. A 7 bit, 2.2 GSsp ADC has been developed by using the voltage to time conversion in dynamic amplifier and the time domain signal folding with logic gates. Our developed 60 GHz CMOS transceiver realized the world´s first 64QAM system and the full four channels 16QAM system and attained the world´s highest data rate of 28 Gbps in 60 GHz wireless communication. Finally we estimated the data rate as a function of the career frequency and TX power. It suggests the importance of the increase of TX power for the further increase of the data rate.