A 8-bit 1-GS/s subranged ADC in 65-nm CMOS process

A digitally subranged analog to digital converter (ADC) using 65nm CMOS process with 1/1.2 of supply voltage is reported in this paper. By employing the charge-pump base background calibrating scheme, the offset voltage from process mismatch could be compensated within three standard deviation less than half of least significant bit (LSB) requirement. A one´s counter base thermal to binary encoder is applied for reducing the impact from random noise. At 1-GS/s sampling rate, the SNR obtained 39.4dB by simulated result at Nyquist frequency. This ADC will occupy an active area of 0.318 um².