A novel algorithm of tail biting convolutional code decoder for low cost hardware implementation

Tail-biting convolutional codes (TBCC) have been applied in many recent modern communication standards such as LTE and WIMAX. TBCC is a method applied in conventional convolutional code by replacing a fixed zero-tail with tail-biting data constrains to achieve a better coding efficiency. This modification makes the decoding process becomes much more complex. Due to impracticality of the optimum decoding algorithm such as brute force, recently some suboptimum algorithms have been developed but it still leaves a large amount of computation due to the iterative nature wherein the number of iterations depends on the received codeword causes inefficient system for implementation, especially for real time applications. In this paper we offer a new algorithm that is specific to low cost hardware implementation. Low cost criteria are addressed to minimum amount of computation for each decoding process. In addition to causing smaller area consumption, the lack of computing process will also make decoding processing time becomes faster. This algorithm that we call reverse trellis algorithm also offers a fixed amount of computation regardless to the received codeword, thus will not require extra memory consumption as it being on an implementation. Taking a case study on TBCC configuration for LTE, proposed algorithm requires 5712 adding operations and 3008 inverting operations. A significant decrease compared to 286736, adding 143360 inverting for Brute Force and 45079976738816 adding 1099511627776 inverting for all possible fixed tail ML decoder. In the performance of BER, reverse trellis algorithm is able to deliver improved by more than 1 dB compared to direct terminating ML decoder.