Design of generic hardware for soft cascade-based linear SVM classification

Support Vector Machine is renowned as a powerful machine learning algorithm for many classification problems. However, among all the works proposed for SVM hardware implementation, a lot of them are designed with predefined settings for specific objective, rendering them usable only for single or few purposes. This paper presents an SVM hardware architecture capable of classifying input data with arbitrary vector dimensionality and arbitrary precision, resulting in a generic support vector machine capable of classifying various targets. The proposed architecture also employs a speed-up method called soft cascade algorithm to enhance its performance. To assess its hardware implementation, it is synthesized in two styles using Xilinx FPGA and NanGate Open Cell Library. The results show a feasible circuit scale implementation, and when used for CoHOG pedestrian detection, the proposed hardware architecture is estimated to be capable of classifying up to 79 VGA images per second on FPGA and up to 35 HD images per second on 45nm process technology circuit, even under the condition that the architecture is not designed specifically for the aforementioned purpose.