NEM relay based multi-nary RAM a memory with optimized power, area and speed

Today, more than half of the transistors inside a processor are dedicated to memory and also they consume most of the power. The CMOS power supply scaling has reached its limit because of leakage current and hence not able to satisfy the increasing modern memory requirements anymore. Nano-electromechanical (NEM) relay is such a device that can offer zero leakage current. The zero leakage operation has generated lot of interest in low power memory design using these relays. In this paper a NEM Relay based multi-nary RAM is proposed that can store multiple bits inside a single cell. The NEM relay based implementation will help to reduce the power and the multi-nary storage technique helps for minimum transistor implementation and their by area optimization.