Reliability challenges in resistive switching memories technology

In this work, the important resistive switching memory (RRAM) parameter tunability is studied in DC and AC switching mode. The tradeoff between these parameters for optimized switching are assessed. The variability in low (LRS) and high (HRS) resistance states in each consecutive pulse SET/RESET cycle is studied. It is found that HRS and LRS read current follow the log-normal and normal distributions, respectively. Endurance test from 1million switching cycles demonstrates that in a small percentage of cycles the set operation may fail, which might be missed if not all the HRS and LRS values are read.