From WLR to product reliability and qualifications in the 3D transistor era

Reliability mechanisms associated with HK+MG transistors including latest FinFETs on 14nm technology node will be discussed along with circuit and product implications on reliabilty stresses and qualifications. Reliability efforts made at the transistor module level to circuit, IP blocks, and finally to a product level reliability will be discussed and limiting mechanisms and examples will be highlighted. As part of the product qual strategy, high-speed HTOL and Set level tests were leveraged to signficantly lower product dpms and seamless introduction of high volume manufacturing.