CRC (Cyclic Redundancy Check) Implementation in High-Speed Semiconductor Memory

This paper presents a CRC scheme for the semiconductor memory devices. Conventional error detecting method by using the ATM-8 HEC code leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC(Cyclic Redundancy Check) calculations. The proposed error detecting scheme is improved area-overhead up to 92% and decreased 2 stage of XOR. The error detection coverage has improved compared with conventional method.