Design and simulation of LNA using 0.18 ?m CMOS technology for UWB systems

This paper presents the UWB LNA using 0.18μm CMOS technology. The proposed circuit is simulated for the frequency range of 3.1GHz to 10.6GHz. By applying the resistive feedback topology, the noise figure of the circuit can be improved. The source degeneration technique helps in balancing the effect of parasitic capacitance. The proposed circuit has the cascade and cascode connections of the transistors helped in the increment of the gain. The simulation results shows that the highest gain of the circuit is 19.982dB at 8.665GHz & the gain is approximately constant throughout the frequency range. The minimum noise figure is 1.270dB at 3.1GHz and the maximum noise figure is 3.4dB at 10.6GHz.