An enhancement transient response of capless LDO with improved dynamic biasing control for SoC applications

This paper presents an enhancement transient capless low dropout voltage regulator (LDO). To eliminate the external capacitor, the miller effect is implemented through the use of a current amplifier. The proposed regulator LDO provides a load current of 50 mA with a dropout voltage of 200 mV, consuming 14μA quiescent current at light loads, and the regulated output voltage is 1.6 V with an input voltage range from 1.2 to 1.8 V. The proposed system is designed in 0.18 μm CMOS technology. A folded cascode amplifier with high transconductance and high power efficiency is proposed to improve the transient response of the LDO. In addition, multiloop feedback strategy employs a direct dynamic biasing technique to provide a high speed path during the load transient responses. The simulation results presented in this paper will be compared with other results of SoC LDOs demonstrate the advantage of the proposed topology.