A new 65nm-CMOS 1V 8GS/s 9-bit differential Voltage-Controlled Delay Unit utilized for a Time-Based Analog-to-Digital Converter circuit

A new differential Voltage-Controlled Delay Unit (VCDU) is proposed. The VCDU converts an input voltage into a pulse delay, and delivers it to a Time-to-Digital Converter (TDC) which outputs a digital word. Both circuits form a Time-Based Analog-to-Digital Converter (ADC). In scaled CMOS technology, the Time-Based ADC is a substantial block in designing Software Defined Radio (SDR) receivers, as it exhibits high speed and low power. The new manually-calibrated differential VCDU circuit operates on a high sampling frequency of 8GS/s in 65nm CMOS technology, with a supply voltage of 1V. It achieves a wide dynamic-range of 0.56V at a 3% linearity error and effective-number-of-bits (ENOB) of 8.9 bits. Additionally, it consumes an area of 742μm² and a power consumption of 1.6mW. A metal-insulator-metal capacitor is used to minimize the process-voltage-temperature variations. The simulation results are compared to single-ended VCDU results and to state-of-the-art analog-part ADCs results to show the strength of the proposed design.