Efficient hardware realization of signed arithmetic operation using IEN

For implementation of a fast arithmetic algorithm and efficient hardware realization, signed digit representation is crucial. Redundant binary (RB) and 2´s complement number representation is the most widely used technique for representation signed digit number. The drawbacks of RB technique include multi valued logic as well as need of unconventional hardware blocks. Though 2´s complement notation is efficient and commonly applicable, it needs further optimization in terms of delay and area. In this paper we proposed binary arithmetic operation using inverted encoding of negabits (IEN), where arithmetic value -1 (0) is represented for 0 (1). The proposed IEN adder is simulated using ISim simulator and synthesized using xc4vlx15-12sf363 FPGA device. The proposed work is verified in terms of utilizing the same hardware blocks as that of conventional signed digit representations. The use of IEN representation advances the signed value in comparison with 2´s complement number representation.