Low-voltage and high-speed CMOS circuit design with low-power mode

In this paper we present a modified ultra-low-voltage and high-speed domino logic style with sleep mode for low-power and low-energy applications. The performance compared to conventional clock voltage switch logic is 15 times higher in terms of speed for a supply voltage equal to 300mV The low-power sleep mode consumes less than 1% of the power in high-performance mode. The CMOS process used for the simulated data presented is 90nm TSMC.