A novel self-referenced ferroelectric-memory readout scheme

Reading one-transistor one capacitor ferroelectric random-access memory (1T-1C FRAM) requires generating a reference voltage that is ideally halfway between the two bitline voltages generated in cases of "1" and "0" readings. However, these two generated voltages vary from cell to cell and with the process variations. So, a self-referenced scheme is needed. In this paper, a self-referenced readout scheme will be proposed that depends on properly pulsing the plateline and using a capacitive-voltage divider. The proposed scheme is verified using simulation adopting the 45 nm CMOS technology and shows a 33% reduction in the read-cycle time. Enhancing the robustness of the reading circuitry will also be investigated quantitatively.