Low power differential three transistors two memristors based RRAM cell

This paper introduces a scheme of three transistors two memristors based memory cell. The write process connects the two memristors in series and the read process connects them in parallel. It utilizes the slowness property of the OFF memristive switching. The scheme uses the differential method of a sense amplifier. The write and read circuit schematics are shown. Simulation results are provided in terms of power and time delay under the use of 45 nm MOSFETs technology and the exponential memristor model. The proposed scheme is power efficient, and it shows good compatibility with the sub-micron MOSFETs models for both write and read processes.