6-Gb/s serial link transceiver for NoCs

This paper introduces the design of a 6-Gb/s serial link for the many core Cairo University SPARC processor. The proposed serial link consists of a serializer and a deserializer. The serializer contains an 8B/10B encoder, a 10:1 multiplexer, a pre-driver, and a driver. The deserializer contains a sampler, a 1:10 demultiplexer, and a 10B/8B decoder. The design is modeled using a digital 65-nm CMOS technology and 1.2-V supply. The use of serial links reduces the interconnect area of the network on chip by 93.96% relative to the design with parallel 32 bit data links. The traces between the cores are modeled using metal layer number eight achieving maximum tolerable clock skew between the transmitter and the receiver up to 49%. The link consumes 1.63 mW power (0.27 pJ/bit).