High performance FIR filter design for 6-input LUT based FPGAs

Advanced FPGA structures contain 6-input LUT tables suitable for the implementation of complex logic functions in a more compact structure. In this paper, high performance fixed coefficient FIR filters are designed by exploiting the advantages of 6-input LUT structures. Using the proposed methodology, fixed coefficient multiplication and accumulation is employed as only two cascades of 6-input LUTs in the critical path. Therefore high performance FIR filtering is possible without any pipelining in the system. For the multiply-accumulate operations only (6, 3) counters are employed together with redundant carry double save operations. 440 MHz clock frequency is reached for the designed 25 tap FIR filter on the Stratix II family FPGA. The proposed arithmetic structure provides more than 90% speed advantage over hardware multiplier based multiply accumulate operations.