DocumentCode :
3763931
Title :
An evaluation of BTI degradation of 32nm standard cells
Author :
Rafael B. Schivittz;Cristina Meinhardt;Paulo F. Butzen
Author_Institution :
Centro de Ci?ncias Computacionais - C3, Universidade Federal do Rio Grande - FURG, Rio Grande, Brasil
fYear :
2015
Firstpage :
661
Lastpage :
664
Abstract :
Aging effects has become a critical reliability constraints in nanometer circuits. The major aging mechanism is the BTI (Bias Temperature Instability), which increases the transistor threshold voltage, reducing system operation frequency and may generate a circuit timing violation. This work presents a tool that estimates the delay degradation due to BTI effect in CMOS logic gates. The work evaluates the delay degradation of a set of the most frequently used combinational gates from a 32nm standard library for different lifetimes. This information is used to define the more sensible gates due to aging effect, providing important information to designer.
Keywords :
"Degradation","Transistors","Logic gates","Delays","Aging","Stress"
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2015 IEEE International Conference on
Type :
conf
DOI :
10.1109/ICECS.2015.7440403
Filename :
7440403
Link To Document :
بازگشت