Switching loss reduction of switched capacitor multilevel inverter using bus clamping modulation

In this paper simulation of three phase structure for recently proposed topology based on self-voltage balancing capability with step up switched capacitor multilevel inverter has been performed in PSCAD software. This topology has simplified gate circuit since number of active switches are less when compared with other switched capacitor topologies. Another advantage is the voltage boost capability with only one voltage source per phase. Sinusoidal Pulse Width Modulation and Bus Clamped Pulse Width Modulation techniques have been considered for both R and RL loads and results have been compared at different modulation indices for both 50 Hz and 400 Hz output voltage. Bus Clamped Pulse Width Modulationis capable of reducing switching losses and gives reduced harmonic distortions even at modulation indices close to unity.