Power reduction techniques used in testing of VLSI circuits

Power consumption during test has become an important issue during manufacturing test because it can lead to the destructive testing and sometimes the problem of wrong response due to overheating may arise, hence it is highly essential to incorporate methods at circuit design phase such that power consumption can be reduced during testing. This paper presents power minimization techniques used in circuits at the logic level of abstraction. Since the presented strategies depends only on controlling primary inputs; power is minimized with no penalty in test area, test efficiency and test application time. The effectiveness of all the discussed techniques has been validated using ISCAS85 benchmark circuits. It has been shown that average 33% of test patterns have been reduced in compaction technique. At the same time test pattern reordering technique reduces 30.02% transitions between two consecutive test patterns. Performance of Bit filling techniques is also studied using ISCAS89 benchmark circuits.