A review on various multipliers designs in VLSI

In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace tree multiplier has the least delay though it also have a large area. We also realized that, with proper optimization the performance of the multipliers can be increased significantly, irrespective of the type. Temporal tilling method optimized array multiplier delay and power dissipation is found to increase by 50% and 30% respectively while using the partially guarded technique power consumption is reduced by 10-44% with 30-36% less area overhead. Booth recorded Wallace tree multiplier is found to be 67% faster than the Wallace tree multiplier, 53% faster than the Vedic multiplier, 22% faster than the radix 8 booth multipliers. We also study various optimization techniques for Wallace multiplier, bypassing multiplier, modified booth multiplier and Vedic multiplier.